This is actually a general question about fetch mode in RTL instructions.
In the 2019 Moed B’s solution to question #4, there is a sketch of RTL fetch mode that looks like this:
What does the green left-bottom path have to do with fetch mode?
Maybe I missed it in Dvir’s recitation but I have watched it again and I still don’t understand it.
The memory controller needs to know the value of PC so it can send the correct instruction into IRenv.
If I get it right, first the PC needs to output the next instruction’s address, and only then it can be sent to the IR. How can this happpen within one clock cycle?
Assuming the clock cycle is long enough, this can be done in one cycle. We haven’t learned timing analysis this year, so this might seem a bit off but the main idea can be understood with the tools we gave (t_pd and t_cont).