In the specifications of the 3:2 adder and 4:2 adder it is written that the outputs should be n+1 and n+2 bits strings respectively (when the inputs are n- bit strings) , but in the file of the project all of these outputs contain only 16 bits (just as much as the inputs).
Why is that? Could it may be a mistake?
That’s because a subset of the outputs is constant zero (just to make everything “rectangular” and simplify the design).
I still don’t understand, can you please explain what do you mean by that?
The inputs and outputs are of width 16, but we’re using the circuits to add strings which are 8 or 9 bits long. The rest is just padding.
So it’s okay that the 4:2 and 3:2 adders won’t handle propely cases in which the input is actually 15/16 bits long (for 3:2 adder and 4:2 adder respectively)?
As long as it handles all strings required in the implementation of the multiplier, it is good enough.