Is it ok to implement a gate which takes more than 2 bits as input?
We are instructed to limit the number of inputs per gate to 2, but should we also limit the number of bits?
For example, is it acceptable to use a not gate which takes a single input of size 6 bits (the bus with 6 zeros in the ztand question)?
You may not use multi-bit gates.
Also, the functionality you require cannot be implemented using multi-bit gates. The way multi-bit gates work is that they implement a logic function between corresponding bits of the two inputs.
For example, if you use a 2-bit AND gate, with A[1:0] and B[1:0], the output C[1:0] is such that
C[0] = A[0] \wedge B[0]\\
C[1] = A[1] \wedge B[1]