As we know, the DLX memory controller can be affected by values in the datapath - for example, the signal AEQZ (which resides in the GPR*) affects the value of bt, which determines the state following BRANCH.
My question is - Since the datapath diagram shows an arrow from the MDR to the memory controller, can it affect its FSM? In other words, can the FSM “read” the bits from the MDR and determine its next state accordingly, without making any modifications to the datapath itself?
If not - how is this any different from AEQZ?
*If I recall correctly, there is a path from AEQZ in the GPR to the memory controller, but it isn’t shown in the diagram.