Project 4 - part 1 - q4

Logisim Projects
1

I’m having a hard time understanding figure 4,
is it possible is this implementation to push one bit and then pop it?
walkthrough (as i understand it):
if i enter first bit 1 (op=01), it instantly arrives at v1 (t=0), after 1 tick (t=1) the bit is between the two FF.
now i try to pop (op=10, t=2, bit 1 is at v2) because of the lag(1), v2 thinks it needs to push, so it pushes it to R_out
only at cycle 3, after the bit has crossed over to v3, it sent back, stuck at the FF before v2,
so if i understand correctly the bit arrives back to v1 only after 4 clock cycles.

this can be resolved if v2 will send the bit both to R_out and v1, regardless of the op.
in this scenario:

  1. do i care about the “rouge” bit crossed to v3?
  2. does the implementation suppose to support modification? meaning popping some of the bits then pushing new ones (in contrast to popping them all together)
    because if it supports modifying, how will v1 choose what bit to push, the one from L_in or the one from v2?

thank you very much

2

I think my question partly arose from the fact that v1 is the only circuit with two inputs without FF (Din, v2),
this complicates the module implementation because it needs to support two cases: the first, and every instance after.

An example to my question will be the input:
image

thank you

3

For whom it may interest,
I think that the output for that example is:
image

In addition, it IS possible, and even mandatory for the implementation to be able to push one bit and then pop it, and:

  1. I guess not
  2. It must support modification, and in that case - it should push L_in, because v2 was already pushed in the previous cycle.

Also, the fact that Din doesn’t have a FF isn’t forcing two implementations.

FYI, I had problem in this question with the op ‘00’, so I strongly encourage everyone to keep an eye open for that one.

Good Luck ! :grin:

4

Same example, but with pauses:
image